Darian Reyes Fernandez de Bulnes
Tijuana Institute of Technology, Mexico
Title: High-Level Synthesis through metaheuristics and LUTs optimization in FPGA devices
Biography
Biography: Darian Reyes Fernandez de Bulnes
Abstract
Operations scheduling and lookup table (LUT) based technology mapping are fundamental problems of mapping designs
onto an electronic device, such as a fi eld programmable gate array. We present an approach to apply two optimizations
consecutively. In fi rst optimization, we apply several metaheuristic algorithms for multi-objective optimization at the high-level
synthesis stage. And in second optimization, we realize reductions of LUTs at the logic synthesis stage. Several circuit designs
are represented in a data fl ow graph (DFG) and the experiments are carried out on the standard Mediabench benchmark. In
the fi rst optimization, we compared NSGA-II, FEMO, HypE, IBEA, SPEA2 and WSGA. Results have an average improvement
14.06% in occupied area and 7.01% in power consumption. Th en, optimized DFG schedules are converted into very high
description language code using the Xilinx ISE design suite tool. Later, in the second optimization, the IMap algorithm is used
to obtain combinational area reductions. Results show that 60% of the circuits are improved in comparison with the Xilinx ISE
design suite.